Interface To External Transceiver (Otg) - Intel PXA27 Series Design Manual

'USB Client Controller
12.4.4

Interface to External Transceiver (OTG)

If the user does not use the internal OTG transceiver, the USB device controller (UDC) contains
control, status, and interrupt registers to provide seamless interface to external transceivers.
External transceivers provide D+, D- and Vbus driver to the USB. In this mode, the D+ and D-
signals of the USB are output through GPIO pads with the
(UP2OCR)"[SE0S] using the control multiplexors to select between:
•
UDC
•
D+, D-, and transmit enable signals of USB host controller
In addition,
•
External transceiver suspend (EXSUS) control output bit
•
External transceiver speed (EXSP) control output bit
•
External transceiver interrupt input to interface to the external transceiver
See Figure 12-6
transceiver.
Figure 12-6. Connection to External OTG Transceiver
1
USB Host
2
Controller
3
Transmit enable
USB Device
Controller
D+/D-
Transmit enable
UP2OCR[EXSUS]
UP2OCR[EXSP]
Ext. Trans. Interrupt
UP2OCR[SEOS]
PXA27x Processor
II:12-8
"USB Port 2 Output Control Register (UP2OCR)"
for illustration of the PXA27x processor OTG connections to an external
USB_P2_4
USB_P2_5
USB_P2_2
USB_P2_8
USB_P2_7
USB_P2_1
"USB Port 2 Output Control Register
provides:
OE_Tp_Int_N
Suspend Enable
Speed Control
ID
External OTG
Transceiver
OTG ID
®
Intel PXA27x Processor Family Design Guide
Dat_VP
SE0_VM
Vbus
Vbus
D +
D +
D -
D -
Interrupt