Bist Result Boundary Scan Register; Boundary Scan Register; Reset Behavior - Intel Pentium II Developer's Manual

Version V
CC
Size 4 1
Binary xxxx 0
Hex x 0
6.4.3.

BIST Result Boundary Scan Register

Holds the results of BIST. It is loaded with a logical 0 on successful BIST completion.
6.4.4.

Boundary Scan Register

Contains a cell for each defined processor signal pin. The following is the bit order of the
cells in the register (left to right, top to bottom). The "Reserved" cells should be left alone.
PWRGOOD should never be driven low during TAP operation.
For more information on Boundary Scan, refer to the Pentium
Description Language files at the Intel developer's website at developer.intel.com.
6.5.

RESET BEHAVIOR

The TAP and its related hardware are reset by transitioning the TAP controller finite state
machine into the Test-Logic-Reset state. Once in this state, all of the reset actions listed in
Table 6-4 are performed. The TAP is completely disabled upon reset (i.e., by resetting the
TAP, the processor will function as though the TAP did not exist). Note that the TAP does
not receive RESET#.
TAP Logic Affected
Instruction Register
Processor boundary scan logic
Processor TDO pin
Table 6-3. Device ID Register
Part Number
Product
Type Generation Model
6 4 5
000001 0110 00011
01 6 03
Table 6-4. TAP Reset Actions
TAP Reset State Action
Loaded with IDCODE op-code
Disabled
Tri-stated
TEST ACCESS PORT (TAP)
Manufacturing
ID "1"
11 1
00000001001 1
09 1
®
II Processor Boundary Scan
Related TAP Instructions
CLAMP, HIGHZ, EXTEST
Entire Code
32
xxxx300000101100
0011000000010011
x02c3013
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6-9