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26.4.5.1
Test-Logic-Reset State
In this state, test logic is disabled to allow the PXA27x processor to operate normally. No matter
what state the controller is in, the PXA27x processor enters the Test-Logic-Reset state when the
TMS input is held high for at least five rising edges of TCK. The controller remains in this state
while TMS is high. Asserting nTRST forces the TAP controller to enter the Test-Logic-Reset state.
If the controller exits the Test-Logic Reset controller state as a result of an erroneous low signal on
the TMS line on the rising edge of TCK (for example, a glitch due to external interference), it
(controller) returns to the Test-Logic-Reset state after three rising edges of TCK with the TMS line
high. Test logic operation does not disturb on-chip logic application as the result of such an error.
26.4.5.2
Run-Test/Idle State
The TAP controller enters the Run-Test/Idle state between scan operations. The controller remains
in this state as long as TMS is held low. Instructions that do not call functions that execute in the
Run-Test/Idle state do not generate any activity in the test logic while the controller is in the Run-
Test/Idle state. The instruction register and all test data registers retain their current states. When
TMS is high on the rising edge of TCK, the controller moves to the Select-DR-Scan state.
26.4.5.3
Select-DR-Scan State
The Select-DR-Scan state is a temporary controller state. The test data register selected by the
current instruction retains its previous state. When the controller is in the Select-DR-Scan state and
TMS is held low on the rising edge of TCK, the controller moves into the Capture-DR state, and a
scan sequence for the selected test data register is initiated. If TMS is held high on the rising edge
of TCK, the controller moves into the Select-IR-Scan state.
The current instruction does not change while the TAP controller is in this state.
26.4.5.4
Capture-DR State
When the controller is in the Capture-DR state and the current instruction is sample/preload, the
boundary-scan register captures input-pin data on the rising edge of TCK. Test data registers that
do not have parallel input are not changed. If the sample/preload instruction is not selected during
this state, the boundary-scan register cells retain their previous states.
The current instruction does not change while the TAP controller is in this state.
If TMS is high on the rising edge of TCK, the controller enters the Exit1-DR state. If TMS is low
on the rising edge of TCK, the controller enters the Shift-DR state.
26.4.5.5
Shift-DR State
In the Shift-DR controller state, the test data register, which is connected between TDI and TDO as
a result of the current instruction, shifts data one bit position nearer to its serial output on each
rising edge of TCK. Test data registers that the current instruction selects but does not place in the
serial path retain their previous values during this state.
The current instruction does not change while the TAP controller is in this state.
If TMS is high on the rising edge of TCK, the controller enters the Exit1-DR state. If TMS is low
on the rising edge of TCK, the controller remains in the Shift-DR state.
®
Intel
PXA27x Processor Family Design Guide
JTAG Debug
II:26-11
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