Pcb Layer Assignment (Stackup) - Intel PXA27 Series Design Manual

PCB Design Guidelines
Table 2-1. Recommended PCB Design Guidelines (Sheet 2 of 2)
Top of Solder Stencil Aperture
Bottom of Solder Stencil
Solder Stencil Thickness
2.2.1

PCB Layer Assignment (Stackup)

See Figure 2-1
illustration shows the recommended PCB layer assignment for an eight-layer PCB using two
power and two ground planes. This configuration provides a continuous VCC_CORE power plane
and a divided I/O power plane for the memory and peripheral domains. See
recommended PCB layer assignment for an eight-layer PCB. See
recommended layout of the divided I/O power plane.
Figure 2-1. 1+6+1 uvia PCB Stackup
External Sig. Layers
1 and 8 50% Copper
¼ oz (9um) + plating
2 thru 7 Copper
For the uvia in pad, design the uvia using RCC (resin-coated copper) surface mount capture pads.
Follow the recommendations for meshing:
•
For internal layers: 70% cu = 50 mil (1.27mm) pitch with 14.6 mil (.37mm) trace width.
•
For external layers: 50% cu = 50 mil (1.27mm) pitch with 22.6 mil (.57mm) trace width.
Follow the recommendations for surface finish and requirements for physical testing:
•
Surface Finish OSP
— Use Organic Solder Preservatives (OSP) Entek 106A.
— Ensure that land pads are as flat as possible (no HASL).
I:2-2
Feature
0.2790 mm/0.0110 inches
0.3000 mm/0.0120 inches
Aperture
0.1270 mm/0.0050 inches
for illustration of the recommended PCB stackup dimensions and materials. The
Internal Layers
Pours 70%
Copper
½ oz (18um)
0.070mm 2.8 mils
VF-BGA
.102mm (4 mil)
µvia copper
plated
Resin Coated Copper
0.13 mm (5.12 mils)
0.13 mm (5.12 mils)
0.13 mm (5.12 mils)
0.13 mm (5.12 mils)
0.13 mm (5.12 mils)
®
Intel PXA27x Processor Family Design Guide
PBGA
0.330 mm/0.013 inches
0.356 mm/0.014 inches
0.127 mm/.005 inches
Figure 2-2 for
Figure 2-3 for illustration of the
0.070mm
2.8 mils
FR4
FR4
.8-1.0mm
FR4
(35 +/-3) mils
FR4
FR4
Resin Coated Copper