Memory Controller Layout Notes; Minimum And Maximum Trace Lengths For The Sdram Signals (Excluding Sdclk<X> And Sdcas) - Intel PXA27 Series Design Manual

System Memory Interface
6.4

Memory Controller Layout Notes

This section contains information for recommended trace lengths, size, and routing guidelines for
both the HD-CSP and FS-CSP configurations. The recommended targeted PCB trace impedance is
60 Ω +15%.
6.4.1 Memory Controller Routing Guidelines for 0.5mm and 0.65
mm Ball Pitch
The following sections describes routing recommendations for HD-CSP using 0.5 mm and 0.65
ball pitch. The guidelines are recommendations and do not guarantee good signal integrity, but are
a good starting point for a working solution.
The subsections describe how to minimize the read cycle hold violation and position clock with
respect to data signal such that it meets both setup and hold requirements and eventually improve
product yield. The recommended topologies are made to improve signal quality.
All guidelines within the section are based on a generic SDRAM driver with a driver impedance
range 25-50 Ω and a rise/fall time range of 1-3 ns.
6.4.1.1 System Bus Recommended Signal Routing Guidelines (Excluding
SDCLK<x> and SDCAS)
The goal is to achieve good signal quality at both driver and receiver as needed. Both data and
clock trace lengths are very sensitive to timing. Lengths beyond the suggested region increases the
risk of having setup or hold violation. The challenge is to deliver a non-monotonic clock to
receivers at SDRAM and return-SDCLK for the PXA27x processor.
Use a balanced-T structure for routing of signals with more than one load. Routing with balanced-
T structure requires more space than daisy chain. This limitation forces the design to add extra
layers in the PCB overall design.
See Table 6-3
connected to the PXA27x processor memory controller, except the clock signals (SDCLKx) and
SDCAS. The trace lengths are based on specific topologies from the memory controller. See
Figure 6-2
Table 6-3. Minimum and Maximum Trace Lengths for the SDRAM Signals (Excluding
SDCLK<x> and SDCAS)
Topology Load
Point-to-point 1 3 - 4"
Balanced-T 2 2 - 3"
Balanced-T 4 1 - 1.5"
Note: Refer to Section 6.4.1.3
II:6-6
for details of the minimum and maximum trace lengths for all memory signals
for illustration of each topology.
L1 L2 L3
NA NA
1 - 1.5" NA
0.5 - 0.75" 0.5 - 0.75"
for information on board stack-up.
PXA27x SDR Driver
Strength Impedance
Code: 4-6
Code: 4-6 25 - 50 ohms
Code: 4-6
®
Intel PXA27x Processor Design Guide
SDR Driver Motherboard
rise/fall times Stack-Up
Micro/strip with
60 Ω +15%
1 - 3 ns
tolerance. 062
board