External Logic For A Two-Socket Configuration Expansion Pc Card - Intel PXA27 Series Design Manual

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System Memory Interface

External Logic for Two-Socket Card Implementation Block Diagram

routed through a buffer to two separate GPIO pins. In the data bus transceiver control logic, nPCE1

controls the enable for the low byte lane and nPCE2 controls the enable for the high byte lane.

Figure 6-11. External Logic for a Two-Socket Configuration Expansion PC Card

PXA27x Memory

for illustration of the glue logic need for a 2-socket system. RDY nBSY signals are

nCE<2:1>, nOE,

PXA27x Processor Design Guide

nCE<2:1>, nOE,

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