Signals - Intel PXA27 Series Design Manual

Interrupt Interface
25.2

Signals

See Table 25-1
are programmable as interrupt signals and, therefore, are used by the interrupt controller.
Table 25-1. GPIO Unit I/O Signal
Signal Name
GPIO<0>
GPIO<1>
GPIO<120:2>
II:25-2
for description of the signals associated with the GPIO Unit. All GPIO unit signals
Type
Causes an independent first-level interrupt
Configured to generate an interrupt by setting ICPR8 bit field.
Input/Output
This signal contains an internal resistive pull-down that are
enabled during power-on, hardware, watchdog, and GPIO resets
and are disabled when PSSR[RDH] is clear
Causes an independent first-level interrupt
Configured to generate an interrupt by setting ICPR9 bit field.
Input/Output
This signal contains an internal resistive pull-up that are enabled
during power-on, hardware, watchdog, and GPIO resets and are
disabled when PSSR[RDH] is clear
Causes an second-level interrupt
Input/Output
These signals cause an interrupt if an edge is detected and
ICPR10 bit field is set.
Description
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Intel PXA27x Processor Family Design Guide
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