Jtag Instruction Register And Instruction Set - Intel PXA27 Series Design Manual

Note: Scan Chains 0 and 1 are not fully JTAG compliant in that data cannot be moved around the chains
without affecting the scan cell outputs. Use these scan chains only in debug state when the core is
not being clocked.conform
Figure 26-2. PXA27x Scan Chain Arrangement
26.4.3

JTAG Instruction Register and Instruction Set

The seven-bit instruction register (IR) holds instruction codes shifted in through the TDI pin.
Instruction codes in this register are used to select the specific test operation to be performed and
the test-data register to be accessed. These instructions are either mandatory, optional, user-
defined, or private, as set forth in the IEEE 1149.1 standard.
The most-significant bit of the IR is connected to TDI and the least-significant bit is connected to
TDO. TDI is shifted into the IR on each rising edge of TCK as long as TMS remains asserted.
When nTRST is asserted, idcode becomes the default instruction.
The PXA27x processor supports the mandatory public boundary-scan instructions, optional public
instructions, user-defined instructions, and private instructions listed in
does not support the IEEE 1149.1 optional public instructions runbist, intest, and usercode. See
Table 26-3
®
Intel PXA27x Processor Family Design Guide
Scan Chain 0
Scan Chain 3
PXA27x
ICEbreaker
Scan Chain 2
•
for description of the supported instructions in detail.
PXA27x Core
•
Scan Chain 1
•
PXA27x TAP
Controller
JTAG Debug
Table 26-2. The processor
II:26-5