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LCD Interface
Figure 7-8. Active Color 18-bit-per pixel Display Typical Connection
7.5.8.3
Layout Notes
Refer to
Section 7.4, "Layout Notes,"
7.5.9
Smart Panel
A smart panel is an LCD panel (which is typically active, but could be passive) that contains the
required frame buffer memory. Having the frame buffer local to the panel requires that the panel
contain much more sophisticated logic than normal LCD panels. These smart panels are equivalent
to simple microcontrollers in capabilities and interface.
Accordingly, the pin interface between the LCD controller on the PXA27x processor and the smart
panel is similar to that of a microcontroller interface. The PXA27x processor uses the same
physical pins as with a normal active or passive panel but with two additions. See
description of the pins used in the connection for smart panels and their functions.
Note: The interface only uses eight data pins (LDD<7:0>). Therefore, three clock cycles transmit one
pixel of information to the panel. Refer to the display manufacturer's documentation for
information on how data is transmitted to the display.
II:7-20
LDD<0>
LDD<1>
LDD<2>
LDD<3>
LDD<4>
LDD<5> MSB of blue
LDD<6>
LDD<7>
LDD<8>
LDD<9>
LDD<10>
LDD<11> MSB of green
LDD<12>
LDD<13>
LDD<14>
LDD<15>
LDD<16>
LDD<17> MSB of red
L_PCLK_WR
L_LCLK_A0
L_FCLK_RD
L_BIAS
for layout notes and considerations.
®
Intel
PXA27x Processor Family Design Guide
B0
B1
B2
B3
B4
B5
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
R5
CLOCK
HORIZ. SYNC
VERT. SYNC
DATA ENABLE
Table 7-11
for
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