Backlight Inverter; Signal Routing And Buffering; Signals .........................................................................................................................Ii: - Intel PXA27 Series Design Manual

LCD Interface
7.4.2

Backlight Inverter

One potential source of noise for the LCD panel is the backlight inverter. Since the backlight
inverter is a high voltage device with frequent voltage inversions, it has the potential to induce
spurious noise in the LCD panel lines. To minimize noise:
•
Use a shielded backlight inverter.
•
Physically place the inverter as far away as possible from the LCD data lines and system board
that are usually located near the LCD panel.
If power consumption is an issue, choose a backlight inverter that disables through software. This
saves power by automatically disabling the backlight if no activity occurs within a preset period of
time.
7.4.3

Signal Routing and Buffering

Signal transmission rates between the LCD controller and the LCD panel are moderate, which
helps to simplify the design of the LCD system. The minimum pixel clock divider (PCD) value
results in a pixel clock rate of one half of the LCLK (this is not the L_LCLK of the LCD
controller.) The maximum LCLK for the PXA27x processor is 104 MHz, resulting in a maximum
pixel clock rate of 52 MHz. Therefore, use of 100 MHz design considerations are sufficient to
ensure LCD panel signal integrity.
However, typical transfer rates are considerably less than 52 MHz. For example, a 800x600 color
active display running at 75 Hz requires a transfer rate of approximately 34 MHz. To determine the
transfer rate, calculate the number of pixels (800 x 600 = 480,000) and multiply by the screen
refresh rate (75 Hz). Since active panels less than 24 bpp in color depth replace 1 pixel of data with
every clock cycle, this determines the final transfer rate. Active displays normally do not require
refresh rates as high as 75 Hz, so use a lower refresh rate to reduce transmission rates even more.
Panels with a color depth of 24 bpp only transfer one third of a pixel per clock cycle. These result
in an LCD clock rate triple that of active panels of the same size.
Passive displays often require refresh rates greater than 75 Hz, but these displays transfer more
pixels for each clock cycle. For instance, a color passive display with eight data lines transfers 2 2/
3 pixels worth of data each clock cycle. This divides the transmission rate by 2 2/3. Further
reductions in the transfer rate come by using dual-scan displays that use twice as many data lines to
transfer data
Generally, this gives lower transfer rates to even larger displays and thus simpler design
considerations and fewer layout constraints.
When laying out your design, minimize trace length of the LCD panel signals and allow sufficient
spacing between signals to avoid crosstalk. Crosstalk decreases the signal integrity, especially the
data line signals.
II:7-4
halving the rate again.
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Intel PXA27x Processor Family Design Guide