External Logic For A One-Socket Configuration Expansion Pc Card - Intel PXA27 Series Design Manual

6.5.6.2.1 External Logic for One-Socket Card Implementation Block Diagram
See Figure 6-10
illustration shows:
•
Data transceivers
•
Address buffers
•
Level shifting buffers
The transceivers are enabled by the PSKTSEL signal. The DIR pin of the transceiver is driven by
the RD/nWR pin. A GPIO is used for the three-state signal of the address and nPWE lines. These
signals must be three-stated because they are used for memories other than the card interface. The
Card Detect<1:0> signals are driven by the single device.
Figure 6-10. External Logic for a One-Socket Configuration Expansion PC Card
PXA27x Processor
MD<15:0>
RD/nWR
GPIO<w>
GPIO<x>
PSKTSEL
GPIO<y>
GPIO<z>
MA<25:0>
nPWE
nPREG
nPCE<2:1>
nPOE
nPIOR
nPIOW
nPWAIT
nIOIS16
®
Intel PXA27x Processor Design Guide
for illustration of the minimal glue logic needed for a 1-socket system. The
DIR
nPCD0
nPCD1
PRDY_BSY0
PADDR_EN0
nOE
5V to 3.3V
5V to 3.3V
System Memory Interface
Socket 0
D<15:0>
nCD<1>
nCD<2>
RDY/nBSY
A<25:0>
nWE
nREG
nCE<2:1>
nOE
nIOR
nIOW
nWAIT
nIOIS16
II:6-27