Sram Block Diagram; Sram Layout Notes; Block Diagram Connecting Sram To Ncs<2 - Intel PXA27 Series Design Manual

System Memory Interface
6.5.4.2

SRAM Block Diagram

See Figure 6-8
memory controller. The particular configuration shown in
it is possible to connect SRAM to any of the nCS signals on the PXA27x processor memory
controller.
Figure 6-8. Block Diagram Connecting SRAM to nCS<2>
6.5.4.3

SRAM Layout Notes

Refer to Section 6.4
®
Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel
Processor Family Electrical, Mechanical, and Thermal Specification for AC timing information.
II:6-20
for illustration of the connection between a SRAM and the PXA27x processor
nCS<5:0>
nOE, nWE
MA<25:1>
DQM<3:0>
MD<31:0>
PXA27x Memory
Controller
for recommendations on trace lengths, size, and routing guidelines. Refer to
Figure 6-8 connects to chip select 2, but
2Mx16
SRAM
2
nCS
nOE
nWE
22:2
A<20:0>
0 DQML
1
DQMH
15:0
DQ<15:0>
2Mx16
SRAM
2
nCS
nOE
nWE
22:2
A<20:0>
2
DQML
3
DQMH
31:16
DQ<15:0>
MEM_004_P2
®
Intel PXA27x Processor Design Guide
®
PXA27x