Figure 3-2. Timing Definitions For Ppc Bus To Sdram Access - Motorola MVME2400 Series Installation And Use Manual

2. The Hawk is configured for "no external registers" on the SDRAM
3. tB1, tB2, tB3, and tB4 are specified in the following figure.
tB4
tB3
tB2
tB1(From Idle)

Figure 3-2. Timing Definitions for PPC Bus to SDRAM Access

Notes
1. When the initial bus state is idle, tB1 reflects the number of CLK
2. When the bus is busy and TS_ is being asserted as soon as possible
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control signals.
periods from the rising edge of the CLK that drives TS_low, to the
rising edge of the CLK that samples the first TA_low.
after Hawk asserts AACK_ the back-to-back condition occurs.
When back-to-back cycles occur, tB1 reflects the number of CLK
periods from the rising edge of the CLK that samples the last TA_
Block Diagram
tB1(Back-to-Back)
3
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