EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
MAIN
PROGRAM
n1
n2
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
i
= INTERRUPT
ii
= INTERRUPT INSTRUCTION WORD
n = NORMAL INSTRUCTION WORD
Figure 7-11 JSR First Instruction of a Fast Interrupt
MOTOROLA
FAST INTERRUPT
VECTOR
JSR
NOT USED
(a) Instruction Fetches from Memory
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
i
i
n1
JSR
—
n1
JSR
NOP
n1
JSR
1
2
3
4
(b) Program Controller Pipeline
PROCESSING STATES
INTERRUPTS RE-ENABLED
ii2
ii3
ii4
iin
RTI
ii2
ii3
ii4
iin
NOP
ii2
ii3
ii4
5
6
7
8
9
LONG INTERRUPT
SUBROUTINE
ii2
ii3
ii4
iin
RTI
—
n2
RTI
NOP
n2
iin
RTI
NOP
n2
10
11
12
13
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