Motorola DSP56000 Manual page 129

Case 2: One of the more common sequences where pipeline effects are apparent is as
follows:
•
•
MOVE #xx,Rn
MOVE X:(Rn),A
•
•
In this case, before the first MOVE instruction has written Rn during its execution cycle,
the second MOVE has accessed the old Rn, using the old contents of Rn. This is
because the address for indirect moves is formed during the decode cycle. This overlap-
ping instruction execution in the pipeline causes the pipeline effect. One instruction cycle
should be allowed after an address register has been written by a MOVE instruction
before the new contents are available for use as an address register by another MOVE
instruction. The proper instruction sequence is as follows:
•
•
MOVE X0,Rn
NOP
•
•
MOVE X:(Rn),A
Case 3: A situation related to Case 2 can be seen in the boot ROM code shown in AP-
PENDIX A of the DSP56001 Technical Data Sheet . At the end of the bootstrap operation,
the operation mode register (OMR) is changed to mode #2, and then the program that was
loaded is executed. This process is accomplished in the last three instructions:
_BOOTEND
The JMP instruction generates its jump address during its decode cycle. If the JMP
instruction followed the MOVEC, the MOVEC instruction would not have changed the
OMR before the JMP instruction formed the fetch address. As a result, the jump would
fetch the instruction at P:$0000 of the bootstrap ROM (MOVE #$FFE9,R2). The OMR
would then change due to the MOVEC instruction, and the next instruction would be the
MOTOROLA
NORMAL PROCESSING STATE
;Move a number into register Rn (n=0–7).
;Use the new contents of Rn to address memory.
;Move a number into register Rn.
;Execute any instruction or instruction
;sequence not using Rn.
Use the new contents of Rn.
MOVEC #2,OMR
ANDI #$0,CCR
JMP <$0
PROCESSING STATES
;Set the operating mode to 2
;(and trigger an exit from
;bootstrap mode).
;Clear SR as if RESET and
;introduce delay needed for
;Op. Mode change.
;Start fetching from PRAM, P:$0000
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