Section 5.1 Program Control Unit; Section 5.2 Overview; Program Address Generator - Motorola DSP56000 Manual

5.1 PROGRAM CONTROL UNIT
This section describes the hardware of the program control unit (PCU) and concludes
with a description of the programming model. The instruction pipeline description is also
included since understanding the pipeline is particularly important in understanding the
DSP56K family of processors.
5.2 OVERVIEW
The program control unit is one of the three execution units in the central processing
module (see Figure 5-2). It performs program address generation (instruction prefetch),
instruction decoding, hardware DO loop control, and exception (interrupt) processing.
The programmer sees the program control unit as six registers and a hardware system
stack (SS) as shown in Figure 5-1. In addition to the standard program flow-control
resources, such as a program counter (PC), complete status register (SR), and SS, the
program control unit features registers (loop address (LA) and loop counter (LC)) dedi-
cated to supporting the hardware DO loop instruction.
The SS is a 15-level by 32-bit separate internal memory which stores the PC and SR for
subroutine calls, long interrupts, and program looping. The SS also stores the LC and LA
registers. Each location in the SS is addressable as a 16-bit register, system stack high
(SSH) and system stack low (SSL). The stack pointer (SP) points to the SS locations.
MOTOROLA
PROGRAM CONTROL UNIT
PAB
CLOCK
INTERRUPTS
CONTROL
OMR
Figure 5-1 Program Address Generator
PROGRAM CONTROL UNIT
PDB
16 24
PC
LA
32 x 15
LC
STACK
SP
SR
24 24
GLOBAL DATA BUS
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