Motorola DSP56000 Manual page 540

INSTRUCTION DESCRIPTIONS
STOP STOP
Stop Instruction Processing
Operation: Assembler Syntax:
Enter the stop processing state and STOP
stop the clock oscillator
Description: Enter the STOP processing state. All activity in the processor is suspended
until the RESET or IRQA pin is asserted. The clock oscillator is gated off internally. The
STOP processing state is a low-power standby state.
During the STOP state, port A is in an idle state with the control signals held inactive (i.e.,
RD=WR=V etc.), the data pins (D0–D23) are high impedance, and the address pins
CC
(A1–A15) are unchanged from the previous instruction. If the bus grant was asserted
when the STOP instruction was executed, port A will remain three-stated until the DSP
exits the STOP state.
If the exit from the STOP state was caused by a low level on the RESET pin, then the
processor will enter the reset processing state. The time to recover from the STOP state
using RESET will depend on the oscillator used. Consult the DSP56001 Advance Infor-
mation Data Sheet (ADI1290) for details.
If the exit from the STOP state was caused by a low level on the IRQA pin, then the pro-
cessor will service the highest priority pending interrupt and will not service the IRQA
interrupt unless it is highest priority. The interrupt will be serviced after an internal delay
counter counts 65,536 clock cycles (or a three clock cycle delay if the stop delay bit in
the OMR is set to one) plus 17T (see the DSP56001 Technical Data Sheet (ADI1290) for
details). During this clock stabilization count delay, all peripherals and external interrupts
are cleared and re-enabled/arbitrated at the start of the 17T period following the count
interval. The processor will resume program execution at the instruction following the
STOP instruction that caused the entry into the STOP state after the interrupt has been
serviced or, if no interrupt was pending, immediately after the delay count plus 17T. If the
IRQA pin is asserted when the STOP instruction is executed, the clock will not be gated
off, and the internal delay counter will be started.
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