Motorola DSP56000 Manual page 409

24-bit digital signal processor
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JSSET
Instruction Format:
JSSET #n,S,xxxx
Opcode:
23
0
0
0
0
Instruction Fields:
#n=bit number=bbbbb,
S=source register=DDDDDD,
xxxx=16-bit Absolute Address in extension word
Source Register
4 registers in Data ALU
8 accumulators in Data ALU
8 address registers in AGU
8 address offset registers in AGU
8 address modifier registers in AGU
8 program controller registers
See Section A.10 and Table A-18 for specific register encodings.
Notes: If A or B is specified as the destination operand, the following sequence of
events takes place:
1. The S bit is computed according to its definition (See Section A.5)
2. The accumulator value is scaled according to the scaling mode bits S0
and S1 in the status register (SR).
3. If the accumulator extension is in use, the output of the shifter is limited to
the maximum positive or negative saturation constant, and the L bit is set.
4. The bit test is performed on the resulting 24-bit value, and the jump to sub-
routine is taken if the bit tested is set. The original contents of A or B are not
changed.
Timing: 6+jx oscillator clock cycles
Memory: 2 program words
MOTOROLA
INSTRUCTION DESCRIPTIONS
Jump to Subroutine if Bit Set
16
15
1
0
1
1
1
1
D
ABSOLUTE ADDRESS EXTENSION
D D D D D D
0 0 0 1 D D
0 0 1 D D D
0 1 0 T T T
0 1 1 N N N
1 0 0 F F F
1 1 1 G G G
INSTRUCTION SET DETAILS
8
7
D
D
D
D
D
0
0
Bit Number bbbbb
JSSET
0
1
b
b
b
b
b
00000
10111
A - 143

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