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PORT A INTERFACE
WT) facility, which allows an external device to insert an arbitrary number of wait states
when accessing either a single location or multiple locations of external memory or I/O
space. Wait states are executed until the external device releases the DSP to finish the
external memory cycle. An internal wait-state generator can be programmed using the
BCR to insert up to15 wait states if it is known ahead of time that access to slower mem-
ory or I/O devices is required. A bus wait signal allows an external device to control the
number of wait states (not limited to 15) inserted in a bus access operation.
MOTOROLA
PORT A
8 - 7
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