Adc - Motorola DSP56000 Manual

ADC

Operation:
S+C+D D (parallel move)
Description: Add the source operand S and the carry bit C of the condition code register
to the destination operand D and store the result in the destination accumulator. Long
words (48 bits) may be added to the (56-bit) destination accumulator.
Note: The carry bit is set correctly for multiple precision arithmetic using long-word op-
erands if the extension register of the destination accumulator (A2 or B2) is the sign
extension of bit 47 of the destination accumulator (A or B).
Example:
:
MOVE L:<$0,X
MOVE L:<$1,A
MOVE L:<$2,Y
ADD X,A L:<$3,B
ADC Y,B A10,L:<$4
MOVE B10,L:<$5
:
Before Execution
A
$FF:800000:000000
X
$800000:000000
B
$00:000000:000001
Y
$000000:000001
Explanation of Example: This example illustrates long-word double-precision (96-bit)
addition using the ADC instruction. Prior to execution of the ADD and ADC instructions,
the double-precision 96-bit value $000000:000001:800000:000000 is loaded into the Y
and X registers (Y:X), respectively. The other double-precision 96-bit value
$000000:000001:800000:000000 is loaded into the B and A accumulators (B:A), respec-
tively. Since the 48-bit value loaded into the A accumulator is automatically sign
extended to 56 bits and the other 48-bit long-word operand is internally sign extended to
56 bits during instruction execution, the carry bit will be set correctly after the execution
of the ADD X,A instruction. The ADC Y,B instruction then produces the correct MS 56-bit
A - 24
INSTRUCTION DESCRIPTIONS
Add Long with Carry
Assembler Syntax:
;get a 48-bit LS long-word operand in X
;get other LS long word in A (sign ext.)
;get a 48-bit MS long-word operand in Y
;add LS words; get other MS word in B
;add MS words with carry, save LS sum
;save MS sum
A
X
B
Y
INSTRUCTION SET DETAILS
ADC S,D (parallel move)
After Execution
$FF:000000:000000
$800000:000000
$00:000000:000003
$000000:000001
ADC
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