Normal Processing State - Motorola DSP56000 Manual

Each instruction requires a minimum of three instruction cycles (12 clock phases) to be
fetched, decoded, and executed. This means that there is a delay of three instruction
cycles on powerup to fill the pipe. A new instruction may begin immediately following the
previous instruction. Two-word instructions require a minimum of four instruction cycles
to execute (three cycles for the first instruction word to move through the pipe and exe-
cute and one more cycle for the second word to execute). A new instruction may start
after two instruction cycles.
The pipeline is normally transparent to the user. However, there are certain instruction-
sequence dependent situations where the pipeline will affect the program execution.
Such situations are best described by case studies. Most of these restricted sequences
occur because 1) all addresses are formed during instruction decode, or 2) they are the
result of contention for an internal resource such as the status register (SR). If the execu-
tion of an instruction depends on the relative location of the instruction in a sequence of
instructions, there is a pipeline effect. To test for a suspected pipeline effect, compare
between the execution of the suspect instruction 1) when it directly follows the previous
instruction and 2) when four NOPs are inserted between the two. If there is a difference,
it is caused by a pipeline effect. The DSP56K assembler flags instruction sequences with
potential pipeline effects so that the user can determine if the operation will execute as
expected.
Case 1: The following two examples show similar code sequences.
1. No pipeline effect:
ORI #xx,CCR
Jcc xxxx
The Jcc will test the bits modified by the ORI without any pipeline effect in the code seg-
ment above.
2. Instruction that started execution during decode:
ORI #04,OMR
MOVE x:$100,a
A pipeline effect occurs in example 2 because the address of the MOVE is formed at its
decode time before the ORI changes the DE bit (which changes the memory map) in the
ORI's execution time slot. The following code produces the expected results of reading
the internal ROM:
ORI #04,OMR
NOP
MOVE x:$100,a
7 - 4

NORMAL PROCESSING STATE

;Changes CCR at the end of execution time slot
;Reads condition codes in SR in its execution time slot
;Sets DE bit at execution time slot
;Reads external RAM instead of internal ROM
;Sets DE bit at execution time slot
;Delays the MOVE so it will read the updated memory map
;Reads internal ROM
PROCESSING STATES MOTOROLA