Two Consecutive Fast Interrupts - Motorola DSP56000 Manual

24-bit digital signal processor
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EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
INTERRUPT SYNCHRONIZED
AND RECOGNIZED
AS PENDING
ADDITIONAL INTERRUPTS
DISABLED DURING
FAST INTERRUPT
INTERRUPTS
RE-ENABLED
ADDITIONAL INTERRUPTS
DISABLED DURING
FAST INTERRUPT
INTERRUPTS
RE-ENABLED
ii = INTERRUPT INSTRUCTION
n = NORMAL INSTRUCTION
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
i
= INTERRUPT
ii
= INTERRUPT INSTRUCTION WORD
n = NORMAL INSTRUCTION WORD
7 - 28
MAIN
PROGRAM
MEMORY
n1
n2
n3
n4
n5
n6
n7
n8
n9
(a) Instruction Fetches from Memory
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
6 I
cyc
i
i
n1
n2
ii1
ii2
n1
n2
ii1
n1
n2
1
2
3
(b) Program Controller Pipeline
Figure 7-9 Two Consecutive Fast Interrupts
PROCESSING STATES
FOUR INSTRUCTION
DECODES
INTERRUPTS RE-ENABLED
i
n3
n4
n5
ii2
n3
n4
ii1
ii2
n3
4
5
6
7
ii1
ii2
ii1
ii2
i
n6
ii1
ii2
n5
n6
ii1
ii2
n4
n5
n6
ii1
ii2
8
9
10
11
12
MOTOROLA

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