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IMMEDIATE SHORT DATA
ADDRESS REGISTER UPDATE
REGISTER TO REGISTER
X MEMORY
X MEMORY PLUS REGISTER
Y MEMORY
Y MEMORY PLUS REGISTER
NOTE: Parallel Move Syntax—Source(Src), Destination(Dst)
Figure 6-15 Classifications of Parallel Data Moves
contents of the 56-bit registers A and B were rounded to 24 bits before moving to the 24-
bit memory registers.
The DSP offers parallel processing of the data ALU, AGU, and program control unit. For
the instruction word above, the DSP will perform the designated operation (data ALU), the
data transfers specified with address register updates (AGU), and will decode the next
instruction and fetch an instruction from program memory (program control unit) all in one
instruction cycle. When an instruction is more than one word in length, an additional
instruction execution cycle is required. Most instructions involving the data ALU are reg-
ister based (all operands are in data ALU registers), thereby allowing the programmer to
keep each parallel processing unit busy. An instruction that is memory oriented (such as
a bit manipulation instruction) or that causes a control-flow change (such as a JMP) pre-
vents the use of parallel processing resources during its execution.
6.4.6 Program Control Instructions
The program control instructions include jumps, conditional jumps, and other instructions
affecting the PC and SS. Program control instructions may affect the CCR bits as speci-
fied in the instruction. Optional data transfers over the XDB and YDB may be specified in
some of the program control instructions. The following list contains the program control
instructions:
DEBUG
Enter Debug Mode
DEBUGcc Enter Debug Mode Conditionally
IIl
Illegal Instruction
Jcc
Jump Conditionally
JMP
Jump
6 - 28
INSTRUCTION GROUPS
OPCODE/OPERANDS
ADD
ADD
ADD
ADD
ADD
ADD
ADD
INSTRUCTION SET INTRODUCTION
PARALLEL MOVE EXAMPLES
X0,A
#$05,Y1
X0,A
(R0)+N0
X0,A
A1,Y0
X0,A
X0,X:(R3)+
X0,A
X:(R4)–,X1
X0,A
Y:(R6)+N6,X0
X0,A
A,X0
A,Y0
B,Y:(R0)
MOTOROLA
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