Trace Exception - Motorola DSP56000 Manual

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
MAIN
PROGRAM
FETCHES
TRACE BIT
n1
SET IN SR
n2
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
i = INTERRUPT
ii = INTERRUPT INSTRUCTION WORD
II = ILLEGAL INSTRUCTION
n = NORMAL INSTRUCTION WORD
MOTOROLA
NEXT TRACE
OPERATION
(a) Instruction Fetches from Memory
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
i
i
n1 NOP NOP NOP JSR
n1 NOP NOP NOP
n1 NOP NOP
1 2 3 4 5 6
(b) Program Controller Pipeline
Figure 7-7 Trace Exception
PROCESSING STATES
TRACE INSTRUCTION n1
NOP
NOP
NOP
JSR
NOT USED
DEBUGGER
PROGRAM
RTI
INTERRUPT SYNCHRONIZED AND
— TRACE PROGRAM RTI —
JSR NOP TRACE PROGRAM RTI
NOP JSR NOP TRACE PROGRAM
7 8 9 10 11 12
THREE NOP
INSTRUCTIONS INSERTED
BY TRACE MODE
FAST INTERRUPT
CAUSED BY TRACE
INTERRUPT
SET TRACE BIT IN SSL
RECOGNIZED AS PENDING
i
i
n2 NOP NOP NOP
NOP n2 NOP NOP NOP
RTI NOP n2 NOP NOP NOP
13 14 15 16 17 18
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