Data Organization In Registers; Data Alu Registers; Operand Sizes - Motorola DSP56000 Manual

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6.3.2 Data Organization in Registers

The ten data ALU registers support 8- or 24-bit data operands. Instructions also support
48- or 56-bit data operands by concatenating groups of specific data ALU registers. The
eight address registers in the AGU support 16-bit address or data operands. The eight
AGU offset registers support 16-bit offsets or may support 16-bit address or data oper-
ands. The eight AGU modifier registers support 16-bit modifiers or may support 16-bit
address or data operands. The program counter (PC) supports 16-bit address operands.
The status register (SR) and operating mode register (OMR) support 8- or 16-bit data
operands. Both the loop counter (LC) and loop address (LA) registers support 16-bit
address operands.
6.3.2.1

Data ALU Registers

The eight main data ALU registers are 24 bits wide. Word operands occupy one register;
long-word operands occupy two concatenated registers. The least significant bit (LSB) is
the right-most bit (bit 0) and the most significant bit (MSB) is the left-most bit (bit 23 for
word operands and bit 47 for long-word operands). The two accumulator extension regis-
ters are eight bits wide.
When an accumulator extension register acts as a source operand, it occupies the low-
order portion (bits 0–7) of the word and the high-order portion (bits 8–23) is sign extended
(see Figure 6-4). When used as a destination operand, this register receives the low-order
portion of the word, and the high-order portion is not used. Accumulator operands occupy
an entire group of three registers (i.e., A2:A1:A0 or B2:B1:B0). The LSB is the right-most
bit (bit 0), and the MSB is the left-most bit (bit 55).
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INSTRUCTION FORMATS
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Figure 6-3 Operand Sizes
INSTRUCTION SET INTRODUCTION
7 0
BYTE
15 0
SHORT WORD
0
WORD
0
LONG WORD
0
ACCUMULATOR
MOTOROLA