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SSL, each 16 bits wide. The SSH stores the PC contents, and the SSL stores the SR con-
tents for subroutine calls, long interrupts, and program looping. The SS will also store the
LA and LC registers. The SS is in stack memory space; its address is always inherent and
implied by the current instruction.
The contents of the PC and SR are pushed on the top location of the SS when a subrou-
tine call or long interrupt occurs. When a return from subroutine (RTS) occurs, the
contents of the top location in the SS are pulled and put in the PC; the SR is not affected.
When an RTI occurs, the contents of the top location in the SS are pulled to both the PC
and SR.
The SS is also used to implement no-overhead nested hardware DO loops. When the DO
instruction is executed, the LA:LC are pushed on the SS, then the PC:SR are pushed on
the SS. Since each SS location can be addressed as separate 16-bit registers (SSH and
SSL), software stacks can be created for unlimited nesting.
The SS can accommodate up to 15 long interrupts, seven DO loops, 15 JSRs, or combi-
nations thereof. When the SS limit is exceeded, a nonmaskable stack error interrupt
occurs, and the PC is pushed to SS location zero, which is not implemented in hardware.
The PC will be lost, and there will be no SP from the stack interrupt routine to the program
that was executing when the error occurred.
5.4.5 Stack Pointer Register
The 6-bit SP register indicates the location of the top of the SS and the status of the SS
(underflow, empty, full, and overflow). The SP register is referenced implicitly by some in-
structions (DO, REP, JSR, RTI, etc.) or directly by the MOVEC instruction. The SP
register format is shown in Figure 5-7. The SP register works as a 6-bit counter that ad-
dresses (selects) a 15-location stack with its four LSBs. The possible SP values are
shown in Figure 5-8 and described in the following paragraphs.
5.4.5.1
Stack Pointer (Bits 0–3)
The SP points to the last location used on the SS. Immediately after hardware reset,
MOTOROLA
PROGRAMMING MODEL
5
4
3
2
1
UF
SE
P3
P2
P1
Figure 5-7 Stack Pointer Register Format
PROGRAM CONTROL UNIT
0
P0
STACK POINTER
STACK ERROR FLAG
UNDERFLOW FLAG
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