The addressing modes are grouped into three categories: register direct, address regis-
ter indirect, and special. These addressing modes are summarized in Table A-2. All
address calculations are performed in the address ALU to minimize execution time and
loop overhead. Addressing modes, which specify whether the operands are in registers,
in memory, or in the instruction itself (such as immediate data), provide the specific
address of the operands.
The register direct addressing mode can be subclassified according to the specific regis-
ter addressed. The data registers include X1, X0, Y1, Y0, X, Y, A2, A1, A0, B2, B1, B0,
A, and B. The control registers include SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR.
Address register indirect modes use an address register Rn (R0–R7) to point to locations
in X, Y, and P memory. The contents of the Rn address register (Rn) is the effective
address (ea) of the specified operand, except in the "indexed by offset" mode where the
effective address (ea) is (Rn+Nn). Address register indirect modes use an address mod-
ifier register Mn to specify the type of arithmetic to be used to update the address regis-
ter Rn. If an addressing mode specifies an address offset register Nn, the given address
offset register is used to update the corresponding address register Rn. The Rn address
register may only use the corresponding address offset register Nn and the correspond-
ing address modifier register Mn. For example, the address register R0 may only use the
N0 address offset register and the M0 address modifier register during actual address
computation and address register update operations. This unique implementation allows
the user to easily address a wide variety of DSP-oriented data structures. All address
register indirect modes use at least one set of address registers (Rn, Nn, and Mn), and
the XY memory reference uses two sets of address registers, one for the X memory
space and one for the Y memory space.
The special addressing modes include immediate and absolute addressing modes as
well as implied references to the program counter (PC), the system stack (SSH or SSL),
and program (P) memory.
Addressing modes may also be categorized by the ways in which they can be used.
Table A-2 and Table A-3 show the various categories to which each addressing mode
belongs. These addressing mode categories may be combined so that additional, more
restrictive classifications may be defined. For example, the instruction descriptions may
use a memory alterable classification, which refers to addressing modes that are both
memory addressing modes and alterable addressing modes. Thus, memory alterable
addressing modes use address register indirect and absolute addressing modes.
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INSTRUCTION SET DETAILS