Long Interrupt Service Routine - Motorola DSP56000 Manual

24-bit digital signal processor
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EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
INTERRUPT
SYNCHRONIZED
AND RECOGNIZED
AS PENDING
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
i
= INTERRUPT
ii
= INTERRUPT INSTRUCTION WORD
n = NORMAL INSTRUCTION WORD
7 - 30
MAIN
PROGRAM
FETCHES
n1
n2
n3
n4
EXPLICIT
RETURN FROM
INTERRUPT
(SHOULD BE RTI)
(a) Instruction Fetches from Memory
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
i
i
n1
n2
ii1
ii2
ii3
n1
n2
ii1
ii2
n1
n2
ii1
1
2
3
4
5
(b) Program Controller Pipeline
Figure 7-10 Long Interrupt Service Routine
PROCESSING STATES
LONG INTERRUPT
SERVICE ROUTINE FETCHES
(STARTS WITH A FAST INTERRUPT)
ii1
ii2
ii3
ii4
INTERRUPT
ROUTINE
ii7
RTI
INTERRUPTS RE-ENABLED
ii4
ii5
ii6
ii7
RTI
ii3
ii4
ii5
ii6
ii7
ii2
ii3
ii4
ii5
ii6
6
7
8
9
10
JSR CAN BE IN EITHER LOCATION
TO FORM A LONG INTERRUPT
PROGRAM COUNTER
RESUMES OPERATION
INTERRUPTS
RE-ENABLED
n3
n4
RTI
NOP
n3
n4
RTI
NOP
n3
n4
ii7
11
12
13
14
15
MOTOROLA

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