Circuit Description - Texas Instruments Chipcon Products CC1000-RTB1 Manual

5. Circuit Description

LNA LNA
RF_IN RF_IN
PA PA
RF_OUT RF_OUT
Figure 1. Simplified block diagram of the
A simplified block diagram of
shown in Figure 1. Only signal pins are
shown.
CC1000
In receive mode
traditional superheterodyne receiver. The
RF input signal is amplified by the low-
noise amplifier (LNA) and converted down
to the intermediate frequency (IF) by the
mixer (MIXER). In
frequency stage (IF
downconverted signal is amplified and
filtered before being
demodulator (DEMOD). As an option a
RSSI signal, or the IF signal after the
mixer is available at the RSSI/IF pin. After
CC1000
demodulation
demodulated data on
Synchronisation is done on-chip providing
data clock at DCLK.
RSSI/IF RSSI/IF
MIXER MIXER
IF STAGE IF STAGE
~ ~
CHARGE CHARGE
VCO VCO
LPF LPF
PUMP PUMP
L1 L1 L2 L2
CHP_OUT CHP_OUT
CC1000
is
is configured as a
the intermediate
STAGE) this
fed to the
outputs the digital
the pin DIO.
SWRS048A
DEMOD DEMOD CONTROL CONTROL
/N /N
PD PD /R /R
CC1000
In transmit mode the voltage controlled
oscillator (VCO) output signal is fed
directly to the power amplifier (PA). The
RF output is frequency shift keyed (FSK)
by the digital bit stream fed to the pin DIO.
The internal T/R switch circuitry makes the
antenna interface and matching very easy.
The frequency synthesiser generates the
local oscillator signal which is fed to the
MIXER in receive mode and to the PA in
transmit mode. The frequency synthesiser
consists of a crystal oscillator (XOSC),
phase detector
(CHARGE PUMP), VCO, and frequency
dividers (/R and /N). An external crystal
must be connected to XOSC, and only an
external inductor is required for the VCO.
The 3-wire digital
(CONTROL) is used for configuration.
CC1000
DIO DIO
DCLK DCLK
PDATA, PCLK, PALE PDATA, PCLK, PALE
3 3
BIAS BIAS
R_BIAS R_BIAS
XOSC_Q2 XOSC_Q2
OSC OSC
XOSC_Q1 XOSC_Q1
(PD), charge pump
serial interface
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