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5 Detailed Description
5.1
Overview
A simplified block diagram of the CC1021 device is shown in
The CC1021 device features a low-IF receiver. The received RF signal is amplified by the low-noise
amplifier (LNA and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF).
At IF, the I/Q signal is complex filtered and amplified, and then digitized by the ADCs. Automatic gain
control, fine channel filtering, demodulation and bit synchronization is performed digitally. The CC1021
device outputs the digital demodulated data on the DIO pin. A synchronized data clock is available at the
DCLK pin. RSSI is available in digital format and can be read via the serial interface. The RSSI also
features a programmable carrier sense indicator.
In transmit mode, the synthesized RF frequency is fed directly to the power amplifier (PA). The RF output
is frequency shift keyed (FSK) by the digital bit stream that is fed to the DIO pin. Optionally, a Gaussian
filter can be used to obtain Gaussian FSK (GFSK).
The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for
generating the LO_I and LO_Q signals to the down-conversion mixers in receive mode. The VCO
operates in the frequency range 1.608 to 1.880 GHz. The CHP_OUT pin is the charge pump output and
VC is the control node of the on-chip VCO. The external loop filter is placed between these pins. A crystal
is to be connected between XOSC_Q1 and XOSC_Q2. A lock signal is available from the PLL.
The 4-wire SPI serial interface is used for configuration.
5.2
Functional Block Diagram
RF_IN
LNA
LNA 2
RF_OUT
PA
PA_EN
Copyright © 2006–2018, Texas Instruments Incorporated
Not Recommended for New Designs NRND
0
:2
90
Power
Control
Multiplexer
BIAS
XOSC_Q1 XOSC_Q2
LNA_EN
R_BIAS
Figure 5-1. CC1021 Device Simplified Block Diagram
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SWRS045F – JANUARY 2006 – REVISED NOVEMBER 2018
Figure
5-1. Only signal pins are shown.
ADC
ADC
0
FREQ
:2
SYNTH
90
XOSC
VC
CHP_OUT
CC1021
CC1021
DIGITAL
DEMODULATOR
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
LOCK
DIO
DCLK
DIGITAL
INTERFACE
PDO
TO mC
PDI
PCLK
PSEL
DIGITAL
MODULATOR
- Modulation
- Data shaping
- Power Control
Detailed Description
15
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