Interrupt Status Register (Rtcisr) - Motorola DragonBall MC68328 User Manual

Real-Time Clock
UNUSED
These bits are not used and read 0.

5.1.4.4 INTERRUPT STATUS REGISTER (RTCISR).

This register indicates the status of the various real-time clock interrupts. Each bit is set
when its corresponding event occurs. Users must clear these bits by writing 1's to clear the
interrupt. The interrupt registers can post interrupts while the system clock is idle (sleep
mode).
15 14 13 12
ADDRESS: $(FF)FFFB0E
UNUSED
These unused bits read 0.
1 Hz FLAG
If enabled, this bit is set every second and an interrupt posted.
1 = 1-Hz interrupt occurred
0 = No 1-Hz interrupt occurred
DAY FLAG
If enabled, this bit is set for every 24-hour clock increment (at midnight) and an interrupt
posted.
1 = 24-hour rollover interrupt occurred
0 = No 24-hour rollover interrupt
ALARM FLAG
If enabled, an alarm flag is set on a "compare" match between the RTC and the alarm reg-
ister value. (Note: the alarm will recur every 24 hours. If a single alarm is required, clear
the interrupt-enable in the interrupt-service routine.)
1 = Alarm interrupt occurred
0 = No alarm interrupt occurred
MIN FLAG
If enabled, a minute flag is set on every minute tick.
1 = Minute tick occurred
0 = No minute tick occurred
5-4 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
11 10 9 8
UNUSED
Figure 5-5. Interrupt Status Register
7 6 5 4
1 Hz
FLAG
3 2 1 0
DAY MIN SW
RVSD
FLAG FLAG FLAG
Reset Value: $0000
MOTOROLA