Panel I/F Timing - Motorola DragonBall MC68328 User Manual

LCD Controller
Shift Clock (LSCLK)
This is the clock output that is synchronized to the LCD panel output data. Users can pro-
gram the LSCLK signal using software to be either active-high or active-low. See the
POLCF register description for details.
Alternate Crystal Direction (LACD)
This output is toggled to alternate the crystal polarization on the panel. Users can program
this signal to toggle at a period of 1 to 16 frames. The alternate crystal direction (LACD,
also called M) pin will toggle after a pre-programmed number of FLM pulses. Users can
program the ACD rate-control register (ACDRC) so that LACD will toggle once every 1 to
16 frames. The targeted number of frames is equal to the alternation code's 4-bit value
plus one. The default value for ACDRC is zero; that is, LACD will toggle on every frame.
The LACD output signal is synchronized with the trailing (falling) edge of the line pulse
(LP) enclosed by FLM.
Table 4-1. ACDRC Value and Number of Cycles

4.3 PANEL I/F TIMING

The LCDC signal continuously pumps the pixel data into the LCD panel via the LCD data
bus. The bus is timed by shift clock (LSCLK), line pulse (LLP) and first line marker (LFLM).
The LSCLK clocks the pixel data into the display drivers' internal-shift register. The LP
latches the shifted pixel data into a wide latch at the end of a line while the LFLM marks the
first line of the displayed page.
The LCDC signal is designed for great flexibility to support most of the monochrome LCD
panels available in the marketplace. Figure 4-3 shows the LCD interface timing for 8-bit LCD
data-bus operations.
Figure 4-3 shows the LCD interface timing for 4-, 2-, and 1-bit LCD data-bus operations.
The line pulse signifies the end of the current line of serial data. The LLP enclosed by LFLM
signal marks the end of the first line of the current frame.
Some LCD panels may use an active-low LFLM signal, LLP signal, LSCLK signal, and
reversed pixel data. To change the polarities of these signals, set the first-line marker polar-
ity (FLMPOL), line-pulse polarity (LPPOL), shift-clock polarity (SCLKPOL), and pixel polarity
4-4 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
ACDRC No of Cycles
0000 1
0001 2
0010 3
0100 5
1000 9
1111 16
MOTOROLA