Pll Control Register; Frequency Select Register - Motorola DragonBall MC68328 User Manual

Phase-Locked Loop and Power Control

3.2.1 PLL Control Register

This register (illustrated in Figure 3-2) controls the overall PLL operation. Several bits are
provided for control of the dynamic performance of the PLL. Refer to Section 3.4.3 for oper-
ation details.
15 14 13 12
UNUSED PIXCLK SEL
Address: $(FF)FFF202
PIXCLK SEL
These bits select the master frequency for the LCD pixel clock. The master clock is de-
rived from the VCO frequency as shown by the list below.
000 = VCO / 2
001 = VCO / 4
010 = VCO / 8
011 = VCO / 16
1XX = VCO / 1 (binary 100 after reset)
SYSCLK SEL
These bits select the master frequency for the MC68328 processor system clock. The
master clock is derived from the VCO frequency as shown by the list below.
000 = VCO / 2
001 = VCO / 4
010 = VCO / 8
011 = VCO / 16
1XX = VCO / 1 (binary 100 after reset)
These bits can be changed at any time. The VCO frequency is unaffected by changes.
CLKEN
This bit enables the CLKO pin while high.
1= CLKO enabled
0= CLKO disabled
DISPLL Disable PLL
This bit, while high, disables the PLL. The system clock is shut down and the MC68328
processor assumes its lowest power state. Only the 32 kHz clock runs. Refer to Section
3.4.3 for a description of the preferred method for system clock shutdown. Once the PLL
is disabled, only a wake-up interrupt or reset can re-enable it.
1 = PLL disabled
0 = PLL enabled

3.2.2 Frequency Select Register

This register (illustrated in Figure 3-3) controls the two dividers of the dual-modulus counter.
One additional bit assists the software to protect the PLL from accidental writes that change
3-2 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
11 10 9 8
SYSCLK SEL
Figure 3-2. PLL Control Register
7 6 5 4
UNUSED CLKEN DISPLL
3 2 1 0
RSVD
Reset Value: $2410
MOTOROLA