Mlt-Master Latency Timer (D0:F0); Hdr-Header Type (D0:F0); Svid-Subsystem Vendor Identification (D0:F0) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

Host Bridge/DRAM Controller Registers (D0:F0)
4.1.7 MLT—Master Latency Timer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Device 0 in the MCH is not a PCI master. Therefore this register is not implemented.
Bit
7:0
4.1.8 HDR—Header Type (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
7:0
4.1.9 SVID—Subsystem Vendor Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This value is used to identify the vendor of the subsystem.
Bit
15:0
52
Access &
Default
Reserved
Access &
Default
RO PCI Header (HDR): This field always returns 0 to indicate that the MCH is a
00h single function device with standard header layout.
Access &
Default
R/WO Subsystem Vendor ID (SUBVID): This field should be programmed during boot-
0000h up to indicate the vendor of the system board. After it has been written once, it
becomes read only.
0
0Dh
00h
RO
8 bits
Description
0
0Eh
00h
RO
8 bits
Description
0
2Ch
0000h
R/WO
16 bits
Description
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Intel 82925X/82925XE MCH Datasheet
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