Ddr2 Dram Channel B Interface - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

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2.3

DDR2 DRAM Channel B Interface

Signal Name
SCLK_B[5:0]
SCLK_B[5:0]#
SCS_B[3:0]#
SMA_B[13:0]
SBS_B[2:0]
SRAS_B#
SCAS_B#
SWE_B#
SDQ_B[63:0]
SDM_B[7:0]
SCB_B[7:0]
®
(Intel 82925X
Only)
SDQS_B[8:0]
(82925X MCH)
SDQS_B[7:0]
(82925XE MCH)
SDQS_B[8:0]#
(82925X MCH)
SDQS_B[7:0]#
(82925XE MCH)
SCKE_B[3:0]
SODT_B[3:0]
®
Intel 82925X/82925XE MCH Datasheet
Type
O SDRAM Differential Clock: (3 per DIMM) SCLK_Bx and its complement
SSTL-1.8 SCLK_Bx# signal make a differential clock pair output. The crossing of
the positive edge of SCLK_Bx and the negative edge of its complement
SCLK_Bx# are used to sample the command and control signals on the
SDRAM.
O SDRAM Complementary Differential Clock: (3 per DIMM) These are
SSTL-1.8 the complementary differential DDR2 clock signals.
O Chip Select: (1 per Rank) These signals select particular SDRAM
SSTL-1.8 components during the active state. There is one chip select for each
SDRAM rank
O Memory Address: These signals are used to provide the multiplexed
SSTL-1.8 row and column address to the SDRAM
O Bank Select: These signals define which banks are selected within
SSTL-1.8 each SDRAM rank
DDR2: 1-Gb technology is 8 banks.
O Row Address Strobe: This signal is used with SCAS_B# and SWE_B#
SSTL-1.8 (along with SCS_B#) to define the SDRAM commands
O Column Address Strobe: This signal is used with SRAS_B# and
SSTL-1.8 SWE_B# (along with SCS_B#) to define the SDRAM commands.
O Write Enable: This signal is used with SCAS_B# and SRAS_B# (along
SSTL-1.8 with SCS_B#) to define the SDRAM commands.
I/O Data Lines: SDQ_Bx signals interface to the SDRAM data bus
SSTL-1.8
2x
O Data Mask: When activated during writes, the corresponding data
SSTL-1.8 groups in the SDRAM are masked. There is one SDM_Bx signal for
2x every data byte lane.
I/O ECC Check Byte: These signals require a 6-layer board to be routed.
SSTL-1.8
2X
I/O Data Strobes: For DDR2, SDQS_Bx and its complement SDQS_Bx#
SSTL-1.8 make up a differential strobe pair. The data is captured at the crossing
2x point of SDQS_Bx and its complement SDQS_Bx# during read and write
transactions.
I/O Data Strobe Complements: These signals are the complementary
SSTL-1.8 DDR2 strobe signals.
2x
O Clock Enable: (1 per Rank) SCKE_B is used to initialize the SDRAMs
SSTL-1.8 during power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
O On Die Termination: Active On-die Termination Control signals for
DDR2 devices.
SSTL-1.8
Signal Description
Description
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