Table 2-5. Clocking Reset And S3 States; Table 2-6. Miscellaneous Reset And S3 States - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet
Express chipset for the intel 82925x/82925xe memory controller hub (mch)
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Also See for 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU:
- Product manual (68 pages) ,
- Specification (34 pages)
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Signal Description
Table 2-5. Clocking Reset and S3 States
Interface
Signal Name
HCLKN
Clocks
HCLKP
GCLKN
GCLKP
DREFCLKN
DREFCLKP
Table 2-6. Miscellaneous Reset and S3 States
Interface
Signal Name
RSTIN#
Misc.
PWROK
EXTTS#
BSEL[2:0]
MTYPE
EXP_SLR
ICH_SYNC#
34
State During
I/O
RSTIN#
Assertion
I
IN
I
IN
I
IN
I
IN
I
IN
I
IN
State During
State After RSTIN#
I/O
RSTIN#
Assertion
I
IN
I
HV
I
PU
I
TRI
I
TERM HV
I
TERM HV
O
PU
§
State After
S3
RSTIN# De-
assertion
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
S3
De-assertion
IN
IN
HV
HV
PU
PU
TRI
TRI
TERM HV
TERM HV
TERM HV
TERM HV
PU
PU
®
Intel
82925X/82925XE MCH Datasheet
R
Pull-up/
Pull-down
Pull-up/
Pull-down
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