Dmivc1Rctl1-Dmi Vc1 Resource Control - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

R
7.1.9 DMIVC1RCTL1—DMI VC1 Resource Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register controls the resources associated with Virtual Channel 1.
Bit
31
30:27
26:24
23:20
19:17
16
15:8
7:1
0
®
Intel 82925X/82925XE MCH Datasheet
Access &
Default
R/W Virtual Channel Enable (EN):
0b
0 = Disable.
1 = Enable.
RO Reserved
0h
R/W Virtual Channel Identifier (ID): This field indicates the ID to use for this virtual
001b channel.
Reserved
R/W Port Arbitration Select (PAS): This field indicates which port table is being
0h programmed. The only permissible value of this field is 4h for the time-based
WRR entries.
RO Load Port Arbitration Table (LAT): When set, the port arbitration table is loaded
0b based upon the PAS field in this register. This bit always returns 0 when read.
Reserved
R/W Transaction Class / Virtual Channel Map (TVM): This field indicates which
00h transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
Reserved
DMIBAR Registers—Direct Media Interface (DMI) RCRB
DMIBAR
020h
00100000h
R/W, RO
32 bits
Description
105