Dmivc1Rsts-Dmi Vc1 Resource Status; Dmilcap-Dmi Link Capabilities - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

Express chipset for the intel 82925x/82925xe memory controller hub (mch)
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DMIBAR Registers—Direct Media Interface (DMI) RCRB
7.1.10
DMIVC1RSTS—DMI VC1 Resource Status
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register reports the Virtual Channel specific status.
Bit
15:2
1
0
7.1.11
DMILCAP—DMI Link Capabilities
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register indicates DMI specific capabilities.
Bit
31:18
17:15
14:12
11:10
9:4
3:0
106
Access &
Default
Reserved
RO
VC Negotiation Pending (NP):
0b
0 = Virtual channel is Not being negotiated with ingress ports.
1 = Virtual channel is still being negotiated with ingress ports.
RO
Port Arbitration Tables Status (ATS): This bit indicates the coherency status of
0b
the port arbitration table.
1 = LAT (offset 000Ch:bit 0) is written with value 1 and PAS (offset
0014h:bits19:17) has value of 4h.
0 = This bit is cleared after the table has been updated.
Access &
Default
Reserved
R/WO
L1 Exit Latency (EL1). L1 not supported on DMI.
010b
R/WO
L0s Exit Latency (EL0): This field indicates that exit latency is 128 ns to less
010b
than 256 ns.
RO
Active State Link PM Support (APMS): This field indicates that L0s is supported
11b
on DMI.
RO
Maximum Link Width (MLW): This field indicates the maximum link width is
4h
4 ports.
RO
Maximum Link Speed (MLS): This field indicates the link speed is 2.5 Gb/s.
1h
DMIBAR
026h
0000h
RO
16 bits
Description
DMIBAR
084h
00012C41h
R/WO, RO
32 bits
Description
®
Intel
82925X/82925XE MCH Datasheet
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