Table 2-3. Pci Express* Graphics X16 Port Reset And S3 States; Table 2-4. Dmi Reset And S3 States - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet
Express chipset for the intel 82925x/82925xe memory controller hub (mch)
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Also See for 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU:
- Product manual (68 pages) ,
- Specification (34 pages)
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R
Interface
Signal Name
SDQS_B[8:0]#
SCKE_B[3:0]
SODT_B[3:0]
SRCOMP0
SRCOMP1
SM_SLEWIN[1:0]
SM_SLEWOU[1:0]
SMVREF[1:0]
SOCOMP[1:0]
NOTES:
1. These signals are on the 82925X MCH only.
2. SDQS_A8/SDQS_A8# and SDQS_B8/SDQS_B8# are on the 82925X MCH only.
Table 2-3. PCI Express* Graphics x16 Port Reset and S3 States
Interface
Signal Name
PCI
EXP_RXN[15:0]
Express*-
EXP_RXP[15:0]
Graphics
EXP_TXN[15:0]
EXP_TXP[15:0]
EXP_COMPO
EXP_COMPI
Table 2-4. DMI Reset and S3 States
Interface
Signal Name
DMI
DMI_RXN[3:0]
DMI_RXP[3:0]
DMI_TXN[3:0]
DMI_TXP[3:0]
®
Intel
82925X/82925XE MCH Datasheet
State During
I/O
RSTIN#
Assertion
2
I/O
TRI
O
LV
O
LV
I/O
TRI
I/O
TRI
I
IN
O
TRI
I
IN
I/O
TRI
State During
I/O
RSTIN#
Assertion
I/O
CMCT
I/O
CMCT
O
CMCT 1.0 V
O
CMCT 1.0 V
I
TRI
I
TRI
State During
I/O
RSTIN#
Assertion
I/O
CMCT
I/O
CMCT
O
CMCT 1.0 V
O
CMCT 1.0 V
State After
RSTIN# De-
assertion
TRI
LV
LV
TRI (after RCOMP)
TRI (after RCOMP)
IN
TRI (after RCOMP)
IN
TRI
State After RSTIN#
De-assertion
CMCT
CMCT
CMCT
CMCT
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
TRI (after RCOMP)
TRI (after RCOMP)
State After RSTIN#
De-assertion
CMCT
CMCT
CMCT
CMCT
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
Signal Description
S3
Pull-up/
Pull-down
TRI
LV
LV
TRI
TRI
IN
TRI
IN
DDR2: 40 Ω
TRI
resistor to
ground
S3
Pull-up/
Pull-down
TRI
TRI
S3
Pull-up/ Pull-
down
33
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