Dmilctl-Dmi Link Control; Dmilsts-Dmi Link Status - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

R
7.1.12 DMILCTL—DMI Link Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register allows control of DMI.
Bit
15:8
7
6:2
1:0
7.1.13 DMILSTS—DMI Link Status
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register indicates DMI status.
Bit
15:10
9:4
3:0
®
Intel 82925X/82925XE MCH Datasheet
Access &
Default
Reserved
R/W Extended Synch (ES):
0h
1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to
entering L0 and extra TS1 sequences at exit from L1 prior to entering L0.
Reserved
R/W Active State Link PM Control (APMC): Indicates whether DMI should enter L0s.
00b
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
Access &
Default
Reserved
RO Negotiated Link Width (NLW): This field is valid only when the link is in the L0,
00h L0s, or L1 states (after link width negotiation is successfully completed).
Negotiated link width is x4 (000100b).
All other encodings are reserved.
RO Link Speed (LS)
1h
Link is 2.5 Gb/s.
DMIBAR Registers—Direct Media Interface (DMI) RCRB
DMIBAR
088h
0000h
R/W
16 bits
Description
DMIBAR
08Ah
0001h
RO
16 bits
Description
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