Le1D-Link Entry 1 Description (D1:F0) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

Host-PCI Express* Graphics Bridge Registers (D1:F0)
8.1.57 LE1D—Link Entry 1 Description (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register provides the First part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
31:24
23:16
15:2
1
0
154
Access &
Default
RO Target Port Number: This field specifies the port number associated with the
00h element targeted by this link entry (Egress Port). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
R/WO Target Component ID: This field indicates the physical or logical component that
00h is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Reserved
RO Link Type: This field indicates that the link points to memory-mapped space (for
0b RCRB). The link address specifies the 64-bit base address of the target RCRB.
R/WO Link Valid:
0b
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
1
150h
00000000h
RO, R/WO
32 bits
Description
®
Intel 82925X/82925XE MCH Datasheet
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