Pcists-Pci Status (D0:F0) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

Host Bridge/DRAM Controller Registers (D0:F0)
4.1.4 PCISTS—PCI Status (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This status register reports the occurrence of error events on Device 0's PCI interface. Since the
MCH Device 0 does not physically reside on Primary PCI, many of the bits are not implemented.
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3:0
50
Access &
Default
RO Detected Parity Error (DPE): Hhardwired to a 0.
0b
R/W/C Signaled System Error (SSE): Software clears this bit by writing a 1 to it.
0b
1 = The MCH Device 0 generated an SERR message over DMI for any enabled
Device 0 error condition. Device 0 error conditions are enabled in the
PCICMD, and ERRCMD registers. Device 0 error flags are read/reset from
the PCISTS, or ERRSTS registers.
R/WC Received Master Abort Status (RMAS): Software clears this bit by writing a 1 to
0b it.
1 = MCH generated a DMI request that receives an Unsupported Request
completion packet.
R/WC Received Target Abort Status (RTAS): Software clears this bit by writing a 1 to
0b it.
1 = MCH generated a DMI request that receives a Completer Abort completion
packet.
RO Signaled Target Abort Status (STAS): The MCH will not generate a Target
0b Abort DMI completion packet or Special Cycle. This bit is not implemented in the
MCH and is hardwired to a 0.
RO DEVSEL Timing (DEVT): These bits are hardwired to "00". Device 0 does not
00b physically connect to Primary PCI. These bits are set to "00" (fast decode) so
that optimum DEVSEL timing for Primary PCI is not limited by the MCH.
RO Master Data Parity Error Detected (DPD): PERR signaling and messaging are
0b not implemented by the MCH; therefore, this bit is hardwired to 0.
RO Fast Back-to-Back (FB2B): Hardwired to 1. Device 0 does not physically
1b connect to Primary PCI. This bit is set to 1 (indicating fast back-to-back
capability) so that the optimum setting for Primary PCI is not limited by the MCH.
Reserved
RO 66 MHz Capable: Does not apply to PCI Express*. Hardwired to 0.
0b
RO Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration
1b software that this device/function implements a list of new capabilities. A list of
new capabilities is accessed via register CAPPTR at configuration address offset
34h. Register CAPPTR contains an offset pointing to the start address within
configuration space of this device where the Capability standard register resides.
Reserved
0
06h
0090h
RO, R/W/C
16 bits
Description
®
Intel 82925X/82925XE MCH Datasheet
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