Deven-Device Enable (D0:F0) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

Host Bridge/DRAM Controller Registers (D0:F0)
4.1.16 DEVEN—Device Enable (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register allows for enabling/disabling of PCI devices and functions that are within the MCH.
Bit
31
30
29
28
27
26:2
1
0
58
Access &
Default
R/W PCIEXBAR Enable (PCIEXBAREN):
0b
0 = The PCIEXBAR register is disabled. Memory read and write transactions
proceed as if there were no PCIEXBAR register. PCIEXBAR bits 31:28 are
R/W with no functionality behind them.
1 = The PCIEXBAR register is enabled. Memory read and write transactions
whose address bits 31:28 match PCIEXBAR 31:28 will be translated to
configuration reads and writes within the MCH. These translated cycles are
routed as shown in the table above.
Reserved
R/W DMIBAR Enable (DMIBAREN):
0b
0 = DMIBAR is disabled and does not claim any memory.
1 = DMIBAR memory mapped accesses are claimed and decoded appropriately.
R/W MCHBAR Enable (MCHBAREN):
0b
0 = MCHBAR is disabled and does not claim any memory.
1 = MCHBAR memory mapped accesses are claimed and decoded
appropriately.
R/W EPBAR Enable (EPBAREN):
0b
0 = EPBAR is disabled and does not claim any memory.
1 = EPBAR memory mapped accesses are claimed and decoded appropriately.
Reserved
R/W PCI Express* Port (D1EN):
1b
0 = Bus 0 Device 1 Function 0 is disabled and hidden. This also gates PCI
Strap Express internal clock (lgclk) and asserts PCI Express internal reset (lgrstb).
dependent
1 = Bus 0 Device 1 Function 0 is enabled and visible.
RO Host Bridge: Bus 0 Device 0 Function 0 can not be disabled and is therefore
1b hardwired to 1.
0
54h
00000019h
R/W
32 bits
Description
®
Intel 82925X/82925XE MCH Datasheet
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