Deap-Dram Error Address Pointer (D0:F0) (Intel 82925X Only) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

R
4.1.17 DEAP—DRAM Error Address Pointer (D0:F0) (Intel
Only)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register contains the address of detected DRAM ECC error(s).
Bit
31:7
6:1
0
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Intel 82925X/82925XE MCH Datasheet
Access &
Default
RO/S Error Address Pointer (EAP): This field is used to store the 128B (Two Cache
0000000h Line) address of main memory for which an error (single bit or multi-bit error) has
occurred. Note that the value of this bit field represents the address of the first
single or the first multiple bit error occurrence after the error flag bits in the
ERRSTS register have been cleared by software. A multiple bit error will overwrite
a single bit error.
Once the error flag bits are set as a result of an error, this bit field is locked and
does not change as a result of a new error.
These bits are reset on PWROK.
Reserved
RO/S 0b Channel Indicator: This bit indicates which memory channel had the error.
0 = Channel A
1 = Channel B
Host Bridge/DRAM Controller Registers (D0:F0)
0
58h
00000000h
RO/S
32 bits
Description
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82925X
59