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Intel 925X manual available for free PDF download: Datasheet
Intel 925X Datasheet (242 pages)
Express Chipset For the Intel 82925X/82925XE Memory Controller Hub (MCH)
Brand:
Intel
| Category:
Computer Hardware
| Size: 2.08 MB
Table of Contents
Table of Contents
3
Revision History
11
Introduction
13
Figure 1-1. Intel 925X/925XE Express Chipset System Block Diagram Example
14
Terminology
15
Reference Documents
16
MCH Overview
16
Host Interface
16
System Memory Interface
17
Direct Media Interface (DMI)
18
PCI Express* Graphics Interface
18
System Interrupts
19
MCH Clocking
20
Power Management
20
Signal Description
21
Figure 2-1. Intel ® 82925X/82925XE MCH Signal Interface Diagram
22
Host Interface Signals
23
Figure 2-1. Intel
26
DDR2 DRAM Channel a Interface
26
DDR2 DRAM Channel B Interface
27
DDR2 DRAM Reference and Compensation
28
PCI Express* X16 Graphics Port Signals
28
Clocks, Reset, and Miscellaneous
29
Direct Media Interface (DMI)
29
Power and Ground
30
Reset States and Pull-Up/Pull-Downs
30
Table 2-1. Host Interface Reset and S3 States
31
Table 2-2. System Memory Reset and S3 States
32
Table 2-3. PCI Express* Graphics X16 Port Reset and S3 States
33
Table 2-4. DMI Reset and S3 States
33
Table 2-5. Clocking Reset and S3 States
34
Table 2-6. Miscellaneous Reset and S3 States
34
Register Description
35
Register Terminology
35
Figure 3-1. Conceptual Intel
37
Platform Configuration
37
General Routing Configuration Accesses
38
Standard PCI Bus Configuration Mechanism
38
Table 3-1. Device Number Assignment for Internal MCH Devices
38
Logical PCI Bus 0 Configuration Mechanism
39
Primary PCI and Downstream Configuration Mechanism
39
Figure 3-2. DMI Type 0 Configuration Address Translation
39
PCI Express* Enhanced Configuration Mechanism
40
Figure 3-3. DMI Type 1 Configuration Address Translation
40
Figure 3-4. Memory Map to PCI Express* Device Configuration Space
41
Figure 3-5. Intel
41
Intel 82925X/925XE MCH Configuration Cycle Flowchart
42
I/O Mapped Registers
43
CONFIG_ADDRESS-Configuration Address Register
43
CONFIG_DATA-Configuration Data Register
44
Table 4-1. Device 0 Function 0 Register Address Map Summary
45
Host Bridge/Dram Controller Registers (D0:F0)
45
Device 0 Function 0 PCI Configuration Register Details
48
VID-Vendor Identification (D0:F0)
48
DID-Device Identification (D0:F0)
48
PCICMD-PCI Command (D0:F0)
49
PCISTS-PCI Status (D0:F0)
50
RID-Revision Identification (D0:F0)
51
CC-Class Code (D0:F0)
51
MLT-Master Latency Timer (D0:F0)
52
HDR-Header Type (D0:F0)
52
SVID-Subsystem Vendor Identification (D0:F0)
52
SID-Subsystem Identification (D0:F0)
53
CAPPTR-Capabilities Pointer (D0:F0)
53
EPBAR-Egress Port Base Address (D0:F0)
54
MCHBAR-MCH Memory Mapped Register Range Base Address (D0:F0)
55
PCIEXBAR-PCI Express* Register Range Base Address (D0:F0)
56
DMIBAR-Root Complex Register Range Base Address (D0:F0)
57
DEVEN-Device Enable (D0:F0)
58
DEAP-DRAM Error Address Pointer (D0:F0) (Intel 82925X Only)
59
DERRSYN-DRAM Error Syndrome (D0:F0) (Intel 82925X Only)
60
DERRDST-DRAM Error Destination (D0:F0) (Intel
61
82925X Only)
61
PAM0-Programmable Attribute Map 0 (D0:F0)
62
PAM1-Programmable Attribute Map 1 (D0:F0)
63
PAM2-Programmable Attribute Map 2 (D0:F0)
64
PAM3-Programmable Attribute Map 3 (D0:F0)
65
PAM4-Programmable Attribute Map 4 (D0:F0)
66
PAM5-Programmable Attribute Map 5 (D0:F0)
67
PAM6-Programmable Attribute Map 6 (D0:F0)
68
LAC-Legacy Access Control (D0:F0)
69
TOLUD-Top of Low Usable DRAM (D0:F0)
70
SMRAM-System Management RAM Control (D0:F0)
71
ESMRAMC-Extended System Management RAM Control (D0:F0)
72
ERRSTS-Error Status (D0:F0)
72
ERRCMD-Error Command (D0:F0)
74
SMICMD-SMI Command (D0:F0)
75
SCICMD-SCI Command (D0:F0)
76
SKPD-Scratchpad Data (D0:F0)
76
CAPID0-Capability Identifier (D0:F0)
77
MCHBAR Registers
79
MCHBAR Register Details
80
C0DRB0-Channel a DRAM Rank Boundary Address 0
80
C0DRB1-Channel a DRAM Rank Boundary Address 1
82
C0DRB2-Channel a DRAM Rank Boundary Address 2
82
C0DRB3-Channel a DRAM Rank Boundary Address 3
82
C0DRA0-Channel a DRAM Rank 0,1 Attribute
83
C0DRA2-Channel a DRAM Rank 2,3 Attribute
83
C0DCLKDIS-Channel a DRAM Clock Disable
84
C0BNKARC-Channel a DRAM Bank Architecture
85
C0DRT1-Channel a DRAM Timing Register
86
C0DRC0-Channel a DRAM Controller Mode 0
88
C1DRB0-Channel B DRAM Rank Boundary Address 0
90
C1DRB1-Channel B DRAM Rank Boundary Address 1
90
C1DRB2-Channel B DRAM Rank Boundary Address 2
90
C1DRB3-Channel B DRAM Rank Boundary Address 3
90
C1DRA0-Channel B DRAM Rank 0,1 Attribute
90
C1DRA2-Channel B DRAM Rank 2,3 Attribute
91
C1DCLKDIS-Channel B DRAM Clock Disable
91
C1BNKARC-Channel B Bank Architecture
91
C1DRT1-Channel B DRAM Timing Register 1
91
C1DRC0-Channel B DRAM Controller Mode 0
91
PMCFG-Power Management Configuration
92
PMSTS-Power Management Status
92
EPBAR Registers-Egress Port Register Summary
93
EP RCRB Configuration Register Details
93
Figure 6-1. Link Declaration Topology
93
Table 6-1. Egress Port Register Address Map
93
EPESD-EP Element Self Description
94
EPLE1A-EP Link Entry 1 Address
95
EPLE1D-EP Link Entry 1 Description
95
EPLE2D-EP Link Entry 2 Description
96
EPLE2A-EP Link Entry 2 Address
97
Table 7-1. DMI Register Address Map Summary
99
DMIBAR Registers-Direct Media Interface (DMI) RCRB
99
Direct Media Interface (DMI) RCRB Register Details
100
DMIVCECH-DMI Virtual Channel Enhanced Capability Header
100
DMIPVCCAP1-DMI Port VC Capability Register 1
100
DMIPVCCAP2-DMI Port VC Capability Register 2
101
DMIPVCCTL-DMI Port VC Control
101
DMIVC0RCAP-DMI VC0 Resource Capability
102
DMIVC0RCTL0-DMI VC0 Resource Control
103
DMIVC0RSTS-DMI VC0 Resource Status
104
DMIVC1RCAP-DMI VC1 Resource Capability
104
DMIVC1RCTL1-DMI VC1 Resource Control
105
DMIVC1RSTS-DMI VC1 Resource Status
106
DMILCAP-DMI Link Capabilities
106
DMILCTL-DMI Link Control
107
DMILSTS-DMI Link Status
107
Table 8-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0)
109
Host-PCI Express* Graphics Bridge Registers (D1:F0)
109
Device 1 Configuration Register Details
112
VID1-Vendor Identification (D1:F0)
112
DID1-Device Identification (D1:F0)
112
PCICMD1-PCI Command (D1:F0)
113
PCISTS1-PCI Status (D1:F0)
114
RID1-Revision Identification (D1:F0)
116
CC1-Class Code (D1:F0)
116
CL1-Cache Line Size (D1:F0)
117
HDR1-Header Type (D1:F0)
117
PBUSN1-Primary Bus Number (D1:F0)
117
SBUSN1-Secondary Bus Number (D1:F0)
118
SUBUSN1-Subordinate Bus Number (D1:F0)
118
IOBASE1-I/O Base Address (D1:F0)
119
IOLIMIT1-I/O Limit Address (D1:F0)
119
SSTS1-Secondary Status (D1:F0)
120
MBASE1-Memory Base Address (D1:F0)
121
MLIMIT1-Memory Limit Address (D1:F0)
122
PMBASE1-Prefetchable Memory Base Address (D1:F0)
123
PMLIMIT1-Prefetchable Memory Limit Address (D1:F0)
124
CAPPTR1-Capabilities Pointer (D1:F0)
124
INTRLINE1-Interrupt Line (D1:F0)
125
INTRPIN1-Interrupt Pin (D1:F0)
125
BCTRL1-Bridge Control (D1:F0)
126
PM_CAPID1-Power Management Capabilities (D1:F0)
128
PM_CS1-Power Management Control/Status (D1:F0)
129
SS_CAPID-Subsystem ID and Vendor ID Capabilities (D1:F0)
130
SS-Subsystem ID and Subsystem Vendor ID (D1:F0)
130
MSI_CAPID-Message Signaled Interrupts Capability ID (D1:F0)
131
MC-Message Control (D1:F0)
132
MA-Message Address (D1:F0)
133
MD-Message Data (D1:F0)
133
PEG_CAPL-PCI Express* Capability List (D1:F0)
134
PEG_CAP-PCI Express*-G Capabilities (D1:F0)
134
DCAP-Device Capabilities (D1:F0)
135
DCTL-Device Control (D1:F0)
136
DSTS-Device Status (D1:F0)
137
LCAP-Link Capabilities (D1:F0)
138
LCTL-Link Control (D1:F0)
139
LSTS-Link Status (D1:F0)
140
SLOTCAP-Slot Capabilities (D1:F0)
141
SLOTCTL-Slot Control (D1:F0)
142
SLOTSTS-Slot Status (D1:F0)
143
RCTL-Root Control (D1:F0)
144
RSTS-Root Status (D1:F0)
145
PEGLC-PCI Express*-G Legacy Control
146
VCECH-Virtual Channel Enhanced Capability Header (D1:F0)
147
PVCCAP1-Port VC Capability Register 1 (D1:F0)
147
PVCCAP2-Port VC Capability Register 2 (D1:F0)
148
PVCCTL-Port VC Control (D1:F0)
148
VC0RCAP-VC0 Resource Capability (D1:F0)
149
VC0RCTL-VC0 Resource Control (D1:F0)
149
VC0RSTS-VC0 Resource Status (D1:F0)
150
VC1RCAP-VC1 Resource Capability (D1:F0)
150
VC1RCTL-VC1 Resource Control (D1:F0)
151
VC1RSTS-VC1 Resource Status (D1:F0)
152
RCLDECH-Root Complex Link Declaration Enhanced Capability Header (D1:F0)
152
ESD-Element Self Description (D1:F0)
153
LE1D-Link Entry 1 Description (D1:F0)
154
LE1A-Link Entry 1 Address (D1:F0)
155
PEGSSTS-PCI Express*-G Sequence Status (D1:F0)
155
System Address Map
157
Figure 9-1. System Address Ranges
158
DOS Range (0H - 9_Ffffh)
159
Figure 9-2. Microsoft MS-DOS* Legacy Address Range
159
Legacy Video Area (A_0000H-B_Ffffh)
159
Expansion Area (C_0000H-D_Ffffh)
160
Table 9-1. Expansion Area Memory Segments
160
Extended System BIOS Area (E_0000H-E_Ffffh)
161
Programmable Attribute Map (PAM) Memory Area Details
161
System BIOS Area (F_0000H-F_Ffffh)
161
Table 9-2. Extended System BIOS Area Memory Segments
161
Table 9-3. System BIOS Area Memory Segments
161
Legacy Address Range
158
Main Memory Address Range (1 MB to TOLUD)
162
Figure 9-3. Main Memory Address Range
162
ISA Hole (15 MB-16 MB)
162
Pre-Allocated Memory
163
Table 9-4. Pre-Allocated Memory Example for 64-MB DRAM and 1-MB TSEG
163
Tseg
163
APIC Configuration Space (Fec0_0000H-Fecf_Ffffh)
164
Figure 9-4. PCI Memory Address Range
164
HSEG (Feda_0000H-Fedb_Ffffh)
165
FSB Interrupt Memory Space (Fee0_0000H-Feef_Ffffh)
165
High BIOS Area
165
PCI Express* Configuration Address Space
165
PCI Express* Graphics Attach
166
AGP DRAM Graphics Aperture
166
System Management Mode (SMM)
167
SMM Space Definition
167
SMM Space Restrictions
168
SMM Space Combinations
168
Table 9-5. SMM Space Table
168
SMM Control Combinations
169
SMM Space Decode and Transaction Handling
169
Processor WB Transaction to an Enabled SMM Address Space
169
Table 9-6. SMM Control Table
169
SMM Access through GTT TLB
170
Memory Shadowing
170
I/O Address Space
170
PCI Express* I/O Address Mapping
171
MCH Decode Rules and Cross-Bridge Address Mapping
171
Legacy VGA and I/O Range Decode Rules
171
PCI Memory Address Range (TOLUD - 4 GB)
163
Functional Description
173
Host Interface
173
FSB GTL+ Termination
173
FSB Dynamic Bus Inversion
173
APIC Cluster Mode Support
174
System Memory Controller
174
Memory Organization Modes
174
Figure 10-1. System Memory Styles
175
Table 10-1. Sample System Memory Organization with Interleaved Channels
175
Table 10-2. Sample System Memory Organization with Asymmetric Channels
175
System Memory Configuration Register Overview
176
DRAM Technologies and Organization
177
Rules for Populating DIMM Slots
177
System Memory Supported Configurations
178
Main Memory DRAM Address Translation and Decoding
178
Table 10-3. DDR2 DIMM Supported Configurations
178
Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode)
179
Table 10-5. DRAM Address Translation (Dual Channel Symmetric Mode)
180
DRAM Clock Generation
181
Suspend to RAM and Resume
181
DDR2 On-Die Termination
181
DDR2 Off-Chip Driver Impedance Calibration
181
PCI Express
182
Transaction Layer
182
Data Link Layer
182
Physical Layer
182
Power Management
183
Clocking
183
Figure 10-2. System Clocking Example
184
Electrical Characteristics
185
Absolute Maximum Ratings
185
Table 11-1. Absolute Maximum Ratings
185
Power Characteristics
186
Figure 12-1. Intel
186
Table 11-2. Non-Memory Power Characteristics
186
Table 11-3. DDR2 Power Characteristics
186
Signal Groups
187
Table 11-4. Signal Groups
187
Figure 12-2. Intel
188
General DC Characteristics
189
Table 11-5. DC Characteristics
189
Ballout and Package Information
193
Ballout
193
Figure 12-1. Intel ® 82925X/82925XE MCH Ballout (Top View: Left Side)
194
Figure 12-2. Intel ® 82925X/82925XE MCH Ballout (Top View: Right Side)
195
Table 12-1. MCH Ballout Sorted by Signal Name
196
Table 12-2. MCH Ballout Sorted by Ball Number
207
Package Information
219
Figure 12-3. MCH Package Dimensions
220
Testability
221
Complimentary Pins
221
Table 13-1. Complimentary Pins to Drive
221
XOR Test Mode Initialization
222
XOR Chain Definition
222
XOR Chains
222
Table 13-2. XOR Chain Outputs
222
Table 13-3. XOR Chain #0
223
Table 13-4. XOR Chain #1
225
Table 13-5. XOR Chain #2
227
Table 13-6. XOR Chain #3
229
Table 13-7. XOR Chain #4
231
Table 13-8. XOR Chain #5
233
Table 13-9. XOR Chain #6
235
Table 13-10. XOR Chain #7
237
Table 13-11. XOR Chain #8
239
Table 13-12. XOR Chain #9
241
Pads Excluded from XOR Mode(S)
242
Table 13-13. XOR Pad Exclusion List
242
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