Le1A-Link Entry 1 Address (D1:F0); Pegssts-Pci Express*-G Sequence Status (D1:F0) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

R
8.1.58 LE1A—Link Entry 1 Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register provides the second part of a Link Entry that declares an internal link to another
Root Complex Element.
Bit
63:32
31:12
11:0
8.1.59 PEGSSTS—PCI Express*-G Sequence Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register provides PCI Express status reporting that is required by the PCI Express
specification.
Bit
63:60
59:48
47:44
43:32
31:28
27:16
15:12
11:0
®
Intel 82925X/82925XE MCH Datasheet
Access &
Default
Reserved
R/WO Link Address: This field indicates memory-mapped base address of the RCRB
0 0000h that is the target element (Egress Port) for this link entry.
Reserved
Access &
Default
Reserved
RO Next Transmit Sequence Number: Value of the NXT_TRANS_SEQ counter.
000h This counter represents the transmit Sequence number to be applied to the next
TLP to be transmitted onto the Link for the first time.
Reserved
RO Next Packet Sequence Number: Packet sequence number to be applied to the
000h next TLP to be transmitted or re-transmitted onto the Link.
Reserved
RO Next Receive Sequence Number: This is the sequence number associated with
000h the TLP that is expected to be received next.
Reserved
RO Last Acknowledged Sequence Number: This is the sequence number
FFFh associated with the last acknowledged TLP.
Host-PCI Express* Graphics Bridge Registers (D1:F0)
1
158h
0000000000000000h
R/WO
64 bits
Description
1
218h
0000000000000FFFh
RO
64 bits
Description
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155