C0Dra0-Channel A Dram Rank 0,1 Attribute; C0Dra2-Channel A Dram Rank 2,3 Attribute - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

R
5.1.5 C0DRA0—Channel A DRAM Rank 0,1 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Attribute Registers define the page sizes to be used when accessing different
ranks. These registers should be left with their default value (all zeros) for any rank that is
unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in
the CxDRA registers describes the page size of a pair of ranks.
Channel and Rank Map:
Channel A Rank 0, 1:
Channel A Rank 2, 3:
Channel B Rank 0, 1:
Channel B Rank 2, 3:
Bit
7
6:4
3
2:0
5.1.6 C0DRA2—Channel A DRAM Rank 2,3 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRA0.
®
Intel 82925X/82925XE MCH Datasheet
108h
109h
188h
189h
Access &
Default
Reserved
R/W Channel A DRAM odd Rank Attribute: This 3 bit field defines the page size of
000b the corresponding rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved
Reserved
R/W Channel A DRAM even Rank Attribute: This 3 bit field defines the page size of
000b the corresponding rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved
MCHBAR
108h
00h
R/W
8 bits
Description
MCHBAR
109h
00h
R/W
8 bits
MCHBAR Registers
83