Dmipvccap2-Dmi Port Vc Capability Register 2; Dmipvcctl-Dmi Port Vc Control - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

Express chipset for the intel 82925x/82925xe memory controller hub (mch)
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R
7.1.3
DMIPVCCAP2—DMI Port VC Capability Register 2
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register describes the configuration of Virtual Channels associated with this port.
Bit
31:24
23:8
7:0
7.1.4
DMIPVCCTL—DMI Port VC Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
Bit
15:4
3:1
0
®
Intel
82925X/82925XE MCH Datasheet
Access &
Default
RO
VC Arbitration Table Offset (ATO): This field indicates that no table is present
00h
for VC arbitration since it is fixed.
Reserved
RO
VC Arbitration Capability: This field indicates that the VC arbitration is fixed in
01h
the root complex. VC1 is highest priority and VC0 is lowest priority.
Access &
Default
Reserved
R/W
VC Arbitration Select: This field indicates which VC should be programmed in
000b
the VC arbitration table. The root complex takes no action on the setting of this
field since there is no arbitration table.
RO
Load VC Arbitration Table (LAT): This field indicates that the table programmed
0b
should be loaded into the VC arbitration table. This bit is defined as read/write with
always returning 0 on reads.
DMIBAR Registers—Direct Media Interface (DMI) RCRB
DMIBAR
008h
00000001h
RO
32 bits
Description
DMIBAR
00Ch
00000000h
R/W, RO
16 bits
Description
101

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