Derrsyn-Dram Error Syndrome (D0:F0) (Intel 82925X Only) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

Host Bridge/DRAM Controller Registers (D0:F0)
4.1.18 DERRSYN—DRAM Error Syndrome (D0:F0) (Intel
Only)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register is used to report the ECC syndromes for each quad word of a 32B-aligned data
quantity read from the DRAM array.
Bit
7:0
60
Access &
Default
RO/S 00h DRAM ECC Syndrome (DECCSYN): After a DRAM ECC error on any QW of the
data chunk resulting from a read command, hardware loads this field with a
syndrome that describes the set of bits associated with the first QW containing an
error. Note that this field is locked from the time that it is loaded up to the time when
the error flag is cleared by software. If the first error was a single bit, correctable
error, then a subsequent multiple bit error on any of the QWs in this read transaction
or any subsequent read transaction will cause the field to be rerecorded. When a
multiple bit error is recorded, the field is locked until the error flag is cleared by
software. In all other cases, an error that occurs after the first error, and before the
error flag, has been cleared by software, will escape recording.
These bits are reset on PWROK.
0
5Ch
00h
RO/S
8 bits
Description
®
Intel 82925X/82925XE MCH Datasheet
R
®
82925X