Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet page 87

R
Bit
6:4
3
2:0
®
Intel 82925X/82925XE MCH Datasheet
Access &
Default
R/W DRAM RAS to CAS Delay (t
010b between a row activate command and a read or write command to that row.
000 = 2 DRAM clocks
001 = Reserved
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
Reserved
R/W DRAM RAS Precharge (t
010b inserted between a row precharge command and an activate command to the
same rank.
000 = 2 DRAM clocks
001 = Reserved
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
Description
). This bit controls the number of clocks inserted
RCD
). This bit controls the number of clocks that are
RP
MCHBAR Registers
87